Assuming the stored value of the RHBD 10T proposal the memory cell is 1 in digital logic

Assuming the stored value of the RHBD 10T proposal
the memory cell is 1 in digital logic, that is, Q = 1, QN = 0, S1 = 1,
and S0 = 0, as shown in Fig. We can easily imagine it
The proposed 10H RHBD memory cell maintains memory continuously
value when the WL is driven by a low voltage (WL = 0). Before normal
read the operation, due to the preload circuits, of the bit line voltages
BL and BLN will be brought to 1 in digital logic. In the reading operation,
WL is in high mode (WL = 1), so two access transistors
N3 and N4 are switched on immediately. Nodes Q, QN, S1 and
S0 saves the stored value and the bit line voltage BL is
nor modified However, the BLN network voltage is reduced
due to the discharge operation through the transistors ON N1 and N3.